Impact of Material Variations on Gate-All-Around Nanowire FETs for Low-Power Applications

The present research resolves scaling problems in advanced technology nodes by designing and analyzing high-k dielectric Gate-All-Around (GAA) silicon nanowire Field-Effect Transistors (FETs). GAA FETs are ideal for sub-5 nm nodes because they offer superior electrostatic control and less short-channel effects than conventional planar and FinFET designs. The ability of high-k dielectrics, such SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, and BaTiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>, to achieve maximum gate capacitance while minimizing leakage currents is being studied. Subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are significantly improved in GAA FETs with HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> and BaTiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> through careful tuning of device design, including channel length and nanowire diameter, as the study shows. These improvements show how GAA designs and high-k materials may be employed to enhance device performance and scalability.