MIPS Pipeline Processor for a DE-10 Board in VHDL

A Pipeline MIPS Processor uses five stages to execute given commands. The five stages are Instruction Fetch (IF), Instruction Decode (ID), Execute Operation (EX), Access Memory (MEM), and Write Back (WB). The objective of this study is to implement this on a DE-10 board in VHDL. Prior to approval of this project there was a lack of articles going over this subject on the IEEE website for using VHDL to make such a processor for the DE-10 in 32 bits. There are articles covering ARM processors, and articles covering the use of Verilog. However, there is a lack of articles on the subject on the IEEE website using MIPS VHDL for a 32-bit Pipeline Processor. Quartus is used to create and simulate a basic 32- bit MIPS Pipeline for the DE-10 using VHDL. The objective of this study is to implement and test a 32-bit MIPS Pipeline for the DE-10 in VHDL. A possible future work can include the implementation of hazard detection with a focus on the control hazard.