A Complementary FET (CFET)-Based NAND Design to Reduce RC Delay

As semiconductor innovation proceeds to scale down, minimizing delays caused by resistance (R) and capacitance (C) in coordinate's circuits gets to be pivotal for moving forward execution. This work proposes a Complementary FET (CFET)-based NAND plan to decrease RC delay in rationale circuits. Conventional CMOS-based plans endure from expanded RC delay due to parasitic capacitances and resistances, particularly as gadget measurements recoil. The CFET design, which coordinating both n-type and p-type transistors in a single gadget, offers a one-of-a-kind arrangement by moving forward drive current, lessening exchanging control, and upgrading generally speed compared to routine CMOS rationale. In this, we show a novel CFET-based NAND entryway that addresses the RC delay by optimizing the resistance and capacitance characteristics through gadget scaling and format procedures. Recreations uncover a noteworthy diminishment in engendering delay and control utilization compared to standard CMOS NAND plans. The CFET-based plan illustrates predominant execution in terms of both speed and vitality productivity, making it a promising candidate for future high-performance rationale circuits. This work gives profitable experiences into the potential of CFETs for overcoming the challenges postured by RC delay in progressed VLSI plans.