A 130 GBaud Four-to-One Analog Multiplexer in 130-nm SiGe BiCMOS

This paper presents a 130 GBaud four-to-one analog multiplexer (AMUX) with four-level pulse-amplitude modulation (PAM-4) in a 130-nm SiGe BiCMOS process. The architecture comprises two stages of the two-to-one AMUX. The four quarter-rate signals are fed into the first-stage AMUX circuit after equalization by continuous-time linear equalizers (CTLE) to produce two-way half-rate signals through time interleaving. The AMUX core circuit of the second stage is based on the Gilbert cell. Compared to the conventional sampling method where the clock signal is centered within 1UI of the data signal, the second-stage AMUX in this design aligns the rising edge of the clock signal with the transition edge of the data signal during sampling. This approach avoids the idle dummy branches in the conventional design, thereby significantly improving the energy efficiency. The AMUX generates two full-rate data signals spaced by 1-UI for subsequent feed-forward equalization (FFE). A two-tap FFE is designed with the transconductance (Gm) cell to compensate for the channel loss. As for the clock chain, the half-rate clock is provided by an external high speed clock source. It will pass through a voltage-controlled delay line (VCDL) to regulate the timing relationship between the clock and data signals in the second stage. And the two-way quarter-rate clocks in quadrature phases need to be generated from the half-rate clock for the two AMUXs in the first stage. Finally, a 130 GBaud PAM-4 signal is generated with a power consumption of 1 W.