A Low-Jitter Fractional- <i>N</i> Digital PLL With Spur Cancellation Based on a Multi-DTC Topology

This work presents a low-jitter and low-spur fractional-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> digital phase-locked loop (PLL) with a multi-path topology, each path having its own digital-to-time converter (DTC) and phase detector (PD). We show that, by driving each DTC with properly shifted quantization error sequences and then combining the PD outputs, the dominant fractional spurs due to DTC non-linearity can be canceled out and a significant reduction in DTC jitter is obtained. A number of background adaptive digital algorithms are introduced to ensure a robust operation across PVT spreads. The implemented PLL prototype, fabricated in a 28 nm CMOS process, has an active area of 0.36 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 17.9 mW. At 9.25 GHz near-integer channels, the measured worst case fractional spur is below -<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</roman> dBc, with an rms jitter of 77.1 fs, leading to -<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">249.7</roman> dB jitter-power figure-of-merit.