A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead

This article presents an NMOS header assist cell (NHAC) that lowers static random access memory (SRAM) minimum operating voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>MIN</roman></sub>) with minimal power overhead for low-power applications, even in the case of increased interconnect resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub>) with technology scaling. The proposed NHAC, featuring a Bitcell-compatible layout, is inserted between cell arrays to supply power by dividing cell-power (CVDD) into sub-arrays without additional dummy cells or white space. NHAC improves write ability even in high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub> cases, thanks to the continuous self-collapse of the CVDD voltage by supplying cell power through NMOS during write operations. The NMOS header in NHAC prevents excessive CVDD voltage collapse, thus ensuring the dynamic data retention stability of column half-selected cells (CHSCs). Additionally, by enabling all NHACs in sleep mode, the CVDD voltage can be clamped below the supply voltage, thereby reducing bitcell retention leakage without additional area costs. SRAM macros with additional resistors were fabricated using a 14 nm FinFET process to measure the impact of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub> on the write assist circuits. NHAC achieves a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>MIN</roman></sub> improvement of 210 mV with 4% power overhead, even in the high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>INT</roman></sub> case. In sleep mode, NHAC reduces bitcell retention leakage by 25% at 0.65 V and up to 61% at 1 V. NHAC demonstrates improved write <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>MIN</roman></sub> similar to transient voltage collapse (TVC) write assist. Additionally, it achieves low-power overhead similar to self-induced voltage collapse (SIC) write assist.