Design and FPGA Implementation of Efficient Multiplier Architecture using Reversible Logic

In the present scenario in wireless communication, portable and mobile devices have consistently demanded the designer to design the device for low power consumption and fastest data path computations at low cost. Power loss and time delay become a major parameter in integrated circuits, which plays a very crucial role in digital signal processing operations in communication systems. One significant issue in the existing system is its binary nature, relying on true or false values without accounting for the nuances and uncertainties present in many real-world situations. In comparison to the current method, the reversible logic-based multiplier is suggested to increase multiplication's speed, area, and power. Reversible logic offers a one-to-one mapping between input and output states, ensuring the preservation of information. Reversible logic circuits are intrinsically more energy-efficient because of this property. The proposed architecture will be synthesized and simulated using Xilinx with various FPGA boards. Finally, compare the results with the existing technique. The synthesis result shows that the speed of proposed multiplier based on reversible logic gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58 %), Vedic Multiplier based on CLA (28.49%), Vedic Multiplier based on RCA (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on HCA (20.10%) and Hybrid multiplier using CSELA (17.81%) and Hybrid Vedic Multiplier (7.15%).