Advances in Negative Capacitance FinFET Technology: Insights into Design Innovations and Performance Enhancements

Because of their improved electrostatic control and lower power consumption, negative capacitance FinFETs, or NC-FinFETs, have attracted a lot of interest in improving the performance of nanoscale semiconductor devices. To improve the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}}$</tex> ratio, this article investigates the integration of gate oxide (GO) topologies within NC-FinFETs, focusing on buried Interfacial GO designs that enhance subthreshold properties. The impact of varying interfacial gate oxide thickness within NC-FinFET structures, embedding the IGO layer O.6m within the channel, improves the ON-OFF current ratio, reduces substrate leakage current, and optimizes the DIBL index. We further examined the impact of dual-k spacers and selective doping to improve capacitance matching and scalability and reviewed spacers' effect on different device configurations. With Hf02 and Air as spacers, NC-FinFET gives SS values of 56.962 mY/dec and 58.830 mV/dec, with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{on}/}\mathrm{I}_{\text{off}}$</tex> ratios nearly <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{8}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{7}$</tex> respectively. Different combinations of spacers have been explored. Air+SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> reflected high SS among all combinations. This Review demonstrates how NC-FinFETs may significantly reduce subthreshold swings and maintain operational stability at high scaling levels, revolutionizing semiconductor design.