Multiplexer SRAM Combination-Based Design of Multiple Combinational Gates for In-Memory Computation

Traditional computing systems based on the Von Neumann architecture face challenges with speed and power consumption. To address this, SRAM is used for fast memory access while minimizing power usage. In-memory computation (IMC) leverages SRAM to perform basic computations, such as NAND and NOR, directly within the memory, improving throughput and reducing power consumption. However, IMC adds area overhead due to the integration of computation within the memory. This paper presents a novel design for NAND, NOR, XOR, and Half Adder (HA) for IMC, implemented using 18nm Fin-FET technology, offering better performance with less area overhead than previous methods.