Power-Area Optimized Multiplier Design using In-Memory Computation

This paper presents a novel multiplier design leveraging In-Memory Computation (IMC) with a Content Addressable Memory (CAM) module and associated processors to achieve high energy efficiency and optimal area utilization. Un-like conventional multipliers that rely on separate memory and processing units, leading to latency and power inefficiencies, the proposed architecture integrates computation within the memory. By utilizing the parallel search and match capabilities of CAM, the design minimizes data movement, reducing power consumption and hardware footprint. Implemented in Verilog HDL and validated using Xilinx VIVADO, the proposed multiplier demonstrates a power reduction of 83.06 % compared to approximate multipliers and 90.09 % relative to accurate multipliers. Additionally, the design achieves a 54.05% reduction in LUT utilization and a 49.23% decrease in flip-flop usage. While a marginal increase in I/O ports and buffer gates utilization is observed due to the CAM module's delay compensation, the results highlight the potential of in-memory computation as a transformative approach for energy-efficient. compact hardware in modern computing systems.