Exploring Circuit Families for Optimizing $3\times 2$ Multiplier: Design and Analyses

This paper presents the design, implementation and analyses of a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\times 2$</tex> multiplier using various circuit families, with the aim of optimizing it for reduced delay, area, and power consumption. A multiplier is one of the most important blocks of many Very Large-Scale Integration (VLSI) applications operating as an arithmetic combinational logic circuit, also known as the digital multiplier for binary digit multiplication. Through simulations, we explored multiple circuit families including CMOS logic circuit, Pass transistor logic circuit, Transmission gate logic circuit, Pseudo NMOS logic circuit, Cascode Voltage Switch Logic (CVSL) circuit, Clocked CMOS (C2MOS) logic circuit, and Dual Threshold Pass Transistor (DTPT) logic circuit. We have performed Monte Carlo and Process, Voltage, and Temperature (PVT) assessing performance, stability, and reliability of the circuits in terms of power and delay. Additionally, we have focused on other parameters like area, transistors used, and Power-Delay Product (PDP). Comparison of simulation results helped to investigate the effectiveness of different circuits in multiplier optimization. We devised a Novel circuit for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\times 2$</tex> multiplier by combining elements from various logic families, yielding superior outcomes across the metrics. Our research reports a comprehensive design and analysis of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\times 2$</tex> multiplier which underscores the thorough optimization of the multiplier, as evidenced by our simulation's outcomes. Notably, our Novel circuit exhibited the least power consumption, moderate delay, and PDP. It gave an optimal balance between transistor count and area utilization. Further, it was observed from the Monte Carlo analyses and PVT analyses that confirmed good stability and reliability of the circuits for real-life conditions. Our study shows the design, analyses, and optimization of the Novel circuit, which outperforms conventional logic circuits in terms of efficiency and robustness.