Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”
This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the overall validity of the results, and the main conclusions of the original article remain unchanged.
Authors
- Sudhakar Pamarti (ORCID: https://orcid.org/0000-0003-1457-7508)
- Mohammadreza Zeinali (ORCID: https://orcid.org/0009-0002-8233-1198)
Institutions
- University of California, Los Angeles (US)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2025-04-24
- DOI
- https://doi.org/10.1109/jssc.2025.3550254
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00