A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance

The design of level shifters for high-voltage and high-speed applications must achieve low propagation delays while maintaining high immunity to power supply slew rates. A novel floating voltage level shifter with rapid operation, high power supply slew tolerance, and almost zero static power consumption is introduced. The conversion principle of the circuit is comprehensively analyzed. Additionally, a series of innovative optimization techniques are implemented to enhance switching speed and power supply slew tolerance, eliminate the asymmetry of rise and fall delays, and reduce power consumption and silicon area. The level shifter is designed using 0.18μm BCD technology, and post-layout simulations are performed by extracting parasitic parameters. The simulation results indicate that, at a level-shifting voltage of 45V, the proposed level-shifter achieves a propagation delay of 0.76ns, 300 V/ns of <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</roman><italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>SSH</i></sub>/<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</roman><italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> slew rate immunity, and a single transition energy of 31.2pJ, with near-symmetrical rise and fall propagation delays.