Enhancing Dopingless TFETs with SiGe Heterojunctions: A Reliability Perspective

This paper presents a novel heterojunction design for a dopant-less tunneling field-effect transistor (DL-TFET) aimed at enhancing the on-state current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(I_{on})$</tex> while addressing the challenge of forming an abrupt tunneling junction without doping. The proposed approach utilizes a silicon-germanium (SiGe) layer to replace silicon in the source region, thereby sharpening the tunneling junction at the source/channel (S/C) interface and significantly improving charge carrier tunneling efficiency. Additionally, the device's reliability was analyzed considering the impact of trapped charges at the silicon dioxide interface. Simulation results demonstrate that the SiGe-based heterostructure DL-TFET offers an efficient and reliable solution for low-power applications in next-generation electronic devices.

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Published
2025-02-20
DOI
https://doi.org/10.1109/icsc64553.2025.10968683
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
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article
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article

Enhancing Dopingless TFETs with SiGe Heterojunctions: A Reliability Perspective

Ashish Kumar, Bandi Venkata Chandan, Kaushal Nigam, M. Bakshi et al.
Advancements in Semiconductor Devices and Circuit Design
article

Enhancing Dopingless TFETs with SiGe Heterojunctions: A Reliability Perspective

Ashish Kumar, Bandi Venkata Chandan, Kaushal Nigam, M. Bakshi, Adil Tanveer, Ashok Vaddeswarapu
article en

Abstract

This paper presents a novel heterojunction design for a dopant-less tunneling field-effect transistor (DL-TFET) aimed at enhancing the on-state current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(I_{on})$</tex> while addressing the challenge of forming an abrupt tunneling junction without doping. The proposed approach utilizes a silicon-germanium (SiGe) layer to replace silicon in the source region, thereby sharpening the tunneling junction at the source/channel (S/C) interface and significantly improving charge carrier tunneling efficiency. Additionally, the device's reliability was analyzed considering the impact of trapped charges at the silicon dioxide interface. Simulation results demonstrate that the SiGe-based heterostructure DL-TFET offers an efficient and reliable solution for low-power applications in next-generation electronic devices.

National Institute of Technology Raipur (IN)
Openalex Percentile: Top 93%
Advancements in Semiconductor Devices and Circuit Design
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Enhancing Dopingless TFETs with SiGe Heterojunctions: A Reliability Perspective — Ashish Kumar, Bandi Venkata Chandan, et al. · (2025) | TGRS Research Map | TGRS