Optimized Channel Length and Off State Current for InAs/Si Heterojunction TFET
this paper contains the Optimization and Comparative study of the Planar Architecture of InAs/Si Heterojunction TFETs. Optimizations performed on the Original Model such as Channel length is reduced to 45nm and Gate Metal overlapping is introduced. Doping concentrations are varied to optimize the electrical device parameter after modifying the physical dimensions of the original model. The Optimized model presented shows some significant improvements such as Reduced off state current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf>) while on state current (Ion) remains same and minimum Subthreshold swing slightly increased to 7.3mV/Dec. I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> by I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ratio is about 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup>. Comparative study with Original Model and other parameters of the optimized model are presented further in the paper.
Authors
- Manisha Bharti (ORCID: https://orcid.org/0000-0003-1640-2621)
- Vandana Devi Wangkheirakpam (ORCID: https://orcid.org/0000-0002-1104-993X)
- Mayank Sachan
Institutions
- National Institute of Technology Manipur (IN)
- National Institute of Technology Delhi (IN)
Publication Details
- Published
- 2025-02-20
- DOI
- https://doi.org/10.1109/icsc64553.2025.10968585
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00