Assessment of a Metal-Strip on Stack Gate Oxide Underlap TFET for Improvement of Analog/RF and Linearity Performance

The work presented in this article investigates the effectiveness of presence of low work function live metal strip in improving the performance in terms of analog/RF and linearity parameters for Live-Strip-Dual-Material Gate-Oxide-Stack Double-Gate TFET (LWLS-DMGOSDG TFET) as compared to conventional DMGOSDG TFET under the influence of underlap of 5nm towards the source end. The analog/RF and linearity Figure of Merits (FoMs) such as transconductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(g_{m})$</tex>, gate-to-source and gate-to-drain capacitances, gain-bandwidth product (GBP), cut-off frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(f_{T})$</tex>, second and third order transconductances, Input Intercept Point (IIP3), Voltage Intercept Point (VIP3) and intermodulation distortion (IMD3) have been considered during the device simulation. The simulation results approve the applicability of the proposed device for low power applications.