Pathways for Retention Boost in Atomic Layer Etched IGZO-Based Capacitorless DRAM

By adopting atomic layer etching as an active patterning technique for InGaZnO (IGZO) based thin-film transistors in a 300-mm fab, we demonstrate 40 nm gate-length two-transistors zero-capacitor (2T0C) dynamic random-access memory (DRAM) devices with retention time > 200 s at 95 ºC. Our extensive 2T0C retention tests clarify that retention property can be boosted by (1) suppression of sidewall metal residues to be extrinsic leakage paths; (2) reduction of the subthreshold leakage by negative hold voltage optimization; (3) optimal gate oxide thickness to avoid gate leakage enhancement. Additionally, by utilizing dedicated large gate-area test devices, we successfully identify the driving mechanisms of gate leakage in write and read transistors as Poole–Frenkel emission and direct tunnelling, respectively. The devices can also achieve endurance > 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles with write time < 10 ns at 95 ºC, satisfying the requirements towards future 2T0C DRAM applications with significantly reduced refresh rate.