Developing Predictive Models and GUI for Area & Power Estimation of PISO Shift Register for FPGAs

Shift registers with Parallel-In Serial-Out (PISO) functionality are essential components in digital electronics. They ease data transmission and minimize the amount of wiring needed by converting parallel data into a serial format, and hence used in digital communications, signal processing, and data storage. The significance of these shift registers and their guiding principles is anticipated to grow as digital technology develops, highlighting the need for a thorough analysis of their design constraints. Hence, area and power being two main design constraints for digital circuits need to be estimated. These estimates can be made using current commercial tools, however doing so requires more time because full design cycles must be followed. Therefore, challenges for designers lie in accurate estimation of resource utilization and power dissipation at the early stages of designing while working under a tight deadline. This paper develops area and power estimation models for PISO shift register circuit using the curve fitting and regression technique in MATLAB. Vivado Design Suite (2014.4) is used to simulate and synthesize these circuits for various input/output (I/O) configurations targeted to Zynq-family Field-Programmable Gate Array (FPGA) device (xc7z020clg484-1). Furthermore, a user-friendly graphical user interface (GUI) is developed using Python Tkinter prompting designers to enter minimum input parameters and providing quick estimates of look-up tables (LUTs), flip-flops (FFs) and total on-chip power. These values predicted using GUI are compared with those obtained using Vivado tool. Comparison results infer that estimation errors lie in a comparable range. Hence, the proposed models and GUI expedite the design process by early and accurate estimation of area and power for FPGA-based PISO shift registers.