Design and Optimization of FinFET Based Baugh-Wooley Multiplier Using PFAL

Multipliers are crucial components in many computational tasks, with their efficiency being vital in various applications. With the evolution of chip technology, FinFET devices present a promising alternative to traditional bulk CMOS, providing advantages in power efficiency and performance. Positive Feedback Adiabatic Logic (PFAL) is another technique aimed at reducing power consumption further. This paper explores the design of the Baugh-Wooley multiplier using PFAL in the context of 18nm FinFET technology, implemented using Cadence Virtuoso Tool. The focus is on understanding the trade-offs between power consumption and performance when integrating PFAL with FinFET technology. While adiabatic logic circuits typically achieve low power dissipation, they often suffer from increased delays.