Design of Energy Efficient SRAM Based In Memory Computing

As the gap between processing speed and memory bandwidth widens, In-Memory Computing (IMC) has emerged as a vital approach to achieve energy-efficient and high-performance computing. The traditional Von Neumann architecture separates memory from computation (CPU/GPU). This research proposes an innovative SRAM-based IMC architecture as a potential solution to the Von Neumann bottleneck. By integrating computational capabilities directly within the memory, this architecture minimizes data movement between memory and processing units, leading to significant reductions in energy consumption and latency. The design features a novel SRAM based IMC, capable of performing all basic Boolean functions within the memory array. This work presents a promising solution for next-generation computing systems, where energy efficiency and high performance are critical requirements. The project utilizes SCL 180nm CMOS technology to implement the proposed SRAM-based IMC architecture.