Enhanced Writability of 4P4N CFET SRAM Cell With Transmission Gates

The conventional complementary field-effect transistor (CFET) static random access memory (SRAM) cell with a 4P2N configuration features two access pMOSFETs, leaving spaces for two nMOSFETs above the access transistors intentionally unused, resulting in suboptimal utilization of available space. To address this, we introduce a split-gate process enabling the fabrication of transmission gates. We propose a novel 4P4N SRAM structure with backside contacts (BCs) that significantly enhances writability while maintaining readability. Compared with 4P2N and 4N2P with BCs, 4P4N has higher read delay and energy consumption but shows 54.7% improvement in write performance over 4P2N and 48.1% over 4N2P. In the case of fast NMOS/slow PMOS (FNSP) under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>T</i></sub> variation at process corners, 4P4N enhances read static noise margin (RSNM) while maintaining strong write static noise margin (WSNM).