Compressor-Based Approach for Power-Optimized Error-Tolerant High Accurate Approximate Multipliers Design and Implementation

A common operation in many different applications is multiplication. The performance of a multiplier can be increased by using compressors. Approximate multipliers fall under Approximate Computing, a developing approach focused on en-hancing power efficiency, reducing area, and minimizing delay in applications that can tolerate acceptable errors. It also trades off the necessity of exact computation for improved performance. By using this approach, power usage can be reduced in applications in which precision is not given much importance. An efficient 8-bit approximate multiplier design is achieved by introducing a approximate compressor. The experimental results demonstrate substantial improvements in an 8-bit multiplier, reducing total power by up to 28.4% versus exact multipliers and 31.71% versus existing designs while decreasing delay by up to 54.93% and 72.15% respectively. The average accuracy is found to be 97.02%. The results not only reduce the power consumption but also maintain acceptable levels of precision, demonstrating that this is an effective solution for modern image processing and signal processing applications. The findings add to what we already know about approximate computing, which is important for future research and development in creating energy-efficient digital systems.