On the Capacitance of Nanosheet Transistors
The capacitance of the gate oxide is a crucial parameter to model the performance of MOSFETs. The traditional expression used to compute it stems from the parallel-plate capacitor formula. While its use is appropriate for planar devices, it has been naturally extended to 3-D devices such as those based on nanosheets even if the geometry is quite different. In this work, we compute numerically the gate oxide capacitance of nanosheet transistors and, observing a nonnegligible discrepancy with the planar model, we propose a simple model that better reproduces the computed capacitance. Then, we investigate the definition of equivalent oxide thickness (EOT), showing that it cannot be strictly used for nonplanar devices: however, our improved model allows us to obtain a useful expression valid for the most common cases. Finally, we generalize the capacitance model to nanosheets with rounded corners.
Authors
- Luca Donetti (ORCID: https://orcid.org/0000-0002-5189-867X)
- C. Sampedro (ORCID: https://orcid.org/0000-0001-8730-2594)
- F. Gámiz (ORCID: https://orcid.org/0000-0002-5072-7924)
- Cristina Medina-Bailón (ORCID: https://orcid.org/0000-0002-4280-3149)
- J. L. Padilla (ORCID: https://orcid.org/0000-0002-2082-5304)
Institutions
- Universidad de Granada (ES)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2025-04-24
- DOI
- https://doi.org/10.1109/ted.2025.3559482
- Citations
- 2
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 1.46