Optimised Power-Efficient Design of Approximate Multiplier Using Approximate Compressor

Approximate computing is a paradigm that aims to trade off computational accuracy for gains in performance, power efficiency, and resource utilization, which is particularly beneficial in Very Large Scale Integration (VLSI) design. This approach can be useful in applications where exact precision is not crucial, such as multimedia processing, machine learning, artificial neural networks (ANNs), Error-Tolerant Applications, Emerging technologies like quantum computing and neuromorphic computing. In this paper, we propose an optimised power-efficient approximate multiplier that utilizes precise 4:2 compressors and approximate 4:2 compressors. The compressor has low power consumption, which decreases the overall power usage of the multiplier. The multiplier's functionality was simulated, and the design was then synthesized in Xilinx ISE (Integrated Synthesis Environment) to analyze and verify its power consumption. The proposed Model 1 and Model 2 approximate multipliers significantly decrease power consumption by 68.62% and 72.289% respectively, accuracy by 70.433% for Model 1 and 97.865% for Model 2 when handling higher 8-bit values compared to the exact multiplier. This reduction in power usage is particularly beneficial for power-constrained application and also the proposed approximate multipliers require significantly fewer LUTs (Look-Up Tables) than the exact multiplier. Approx-imate multipliers can be effectively utilized in image processing applications where computational efficiency is crucial and slight errors in calculations can be tolerated.