Implementation of High Speed Cascode Cross-Coupled Stage Comparator in CMOS Technology

Low power dynamic comparator is generally used in ultra-low power applications. This device uses ‘28nm CMOS technology’ and the ‘Power Supply Voltage’ is “l.1V”. In order to reduce “Static Power Consumption” and increase comparison ‘Speed’ most dynamic comparators use a pair of cross-coupled inverters as latch level. This provides a decent power input. Here used double tail latch comparator with cross coupled gives the advantages in the power consumption and input referred RMS noise. Unlike traditional architectures, adding cross-connectors to different pairs of inputs prevents end-to-end comparison of nodes. Reducing the overall effect of the stage, the delay of the rate is decided by the total conductance value of the cross-coupled logics of the comparator transistors with a gate-to-source voltage of zero. This work presents a novel low voltage cascode cross-section and high contrast circuit using CMOS technology. The design concept does not use the standard cross-coupled inverter architecture, but uses gate blocking cross-coupled transistors. This concept increases the overall transconductance value at the beginning of the comparison stage, resulting in faster comparison and lower power consumption. Through simulation and measurement, the “Delay” and “Power Consumption” of the compared products are analyzed and compared with previous models. Test results show that the comparator is recommended to be used from a 1.2V power supply with reference voltage 1-2V consumes less energy.