Design and Simulation of Low Power Leakage-Controlled SRAM Cell

Since the dawn of the 21st century, the rise of IoT-powered portable devices has sparked a revolution in low-power SRAM development. As the complexity of such devices has exponentially increased to support a higher number of operations, advanced power management techniques are now essential to minimize power consumption. Consequently, low-power circuit design continues to be a prominent area of research. This paper introduces an innovative low-power SRAM cell design that surpasses traditional options. Compared to conventional 6T SRAM and DTMOS-based SRAM cells, simulations demonstrate that the proposed design significantly reduces power consumption without compromising propagation delay, marking a promising advancement in SRAM technology. The simulations were conducted using the Siemens Tanner EDA Tool version 2022.2. The supply voltage and operating frequency were set to 2V and 100MHz, respectively.