Analyzing Trap Charge Impact in Dopant Hetero-Material TFET via Interface Engineering

Enhancing the performance of Tunnel Field-Effect Transistors (TFETs) requires the formation of a sharp tunneling junction. This challenge is particularly significant in doped-TFETs (D-TFETs). To address this, we propose a novel hetero-dielectric and hetero-junction design for a D-TFET, utilizing silicon-germanium (SiGe) in the source region. The proposed design enables the creation of a sharper tunneling junction at the source/channel (S/C) interface, resulting in a higher tunneling generation rate of charge carriers. Furthermore, device reliability was evaluated under the influence of trapped charges at the oxide interface, demonstrating the potential of the proposed hetero-structure for low-power electronic applications.