Leveraging AI and ML to transform Twinscan into an inline macro defect inspection system

Over the past few years, the throughput of ASML/TEL lithography clusters has dramatically increased, now exceeding 4,000 wafers per day. While this is a significant achievement that helps the semiconductor industry maintain the cost of advanced technology nodes at a reasonable level, it poses a significant challenge for inline defectivity control using traditional sampling schemes. Any problem detected during a sampling episode can translate into many wafers at risk, causing major disturbances in Fab operations. ASML Twinscan scanners are equipped with sophisticated sensors, such as the optical Level Sensor (LS), which reads the wafer topside topography before exposure to ensure perfect imaging focus. We repurpose these wafer topography data, apply Active Noise Cancellation (ANC) techniques, and use Machine Learning (ML) algorithms to detect any macro defects present on the wafer. This enables a new macro defect inspection capability for semiconductor Fabs with ideal features such as full lot inspection, full wafer inspection, no productivity loss, and no additional cost. Since there are usually many lithography steps throughout the entire wafer process flow, identifying the defect root cause becomes easier. At STMicroelectronics Crolles300 Fab, we developed a software solution named eLitho and deployed it across all our lithography clusters. It has been operational for one and a half years, achieving many successes and receiving internal recognition. We will demonstrate that this is a significant step in our efforts to integrate AI and ML into semiconductor manufacturing, enhance quality, and create additional value for our business and customers. Many more opportunities with AI and ML are on the horizon.