Via to line-end contact failures: the role of stochastics

For the most advanced semiconductor manufacturing nodes, edge placement errors are typically dominated by stochastics, necessitating a rigorous stochastics approach to modeling and measuring edge placement errors and their contributors. In this work, voltage contrast (VC) measurements were used to validate an analytical failure prediction model based on stochastic modeling of a via to line-end contact failure. A specialized mask was developed with designed-in variation in tip-to-tip distance between line-ends and via shifts to produce test wafers in a dual damascene-like process flow with a metal layer pitch of 28nm. SEM measurements were then made alongside VC measurements to match the predicted failure rates with only a single free parameter in the analysis, the via/line-end overlap area threshold for failure. Good linearity and matching were achieved between predicted and measured failure rates over approximately three orders of magnitude. The product of the nominal via area and the optimal threshold parameter determined by minimizing root sum squares of the differences resulted in an absolute overlap area between via and line-end of 172nm². The excellent fit of the analytical model to voltage contrast data means that the calibrated model can be used to make decisions regarding design, process development, and manufacturing trade-offs.