3D metrology and inspection to enable the rise of stacked transistors, wafers, and chips

A critical trend in today’s semiconductor technology is the usage of the 3rd, i.e. vertical, dimension. Although lateral x-y scaling is alive and kicking as demonstrated by the ongoing deployment of High Numerical-Aperture EUV lithography, leveraging the vertical dimension as an extra degree of freedom to squeeze more functionality into the same Si surface area is gaining immense traction. The introduction of 3DNAND flash memories a decade ago only announced the rise of stacked devices, wafers and chips. Today, examples of monolithic and sequential stacking are indeed countless, with applications in both the memory and logic segments and obviously in 3D integration which is its cornerstone. This paper presents our views on the implications of this technology trend on the field of semiconductor metrology and inspection (M&I). We conclude with a call for more collaboration within the M&I ecosystem to provide and test new techniques, which appears to us a critical condition to the further deployment of 3D devices.