On-product, on-device overlay breakdown by layer and contributor using a high-voltage scanning electron microscope

Meeting stricter on-product overlay requirements necessitates a comprehensive understanding of the factors that contribute to overlay errors. A detailed examination of the overlay error contributors at the wafer-level, field-level, and highly localized level, which can vary over the micrometer length scale, forms the basis for such improvement. In this paper, we investigate on-target and on-device overlay across different length scales and time domains using a high-voltage scanning electron microscope (HV-SEM) that employs KLA’s model-based e-beam physics algorithm (ePhysX™) for our analyses. We analyze the individual overlay error contributors by tracking multiple wafers through the process, applying a novel method to measure overlay post-litho inspection (ADI) and after-etch inspection (AEI) at multiple layer steps. Our study encompasses the effects from multiple scanners, lots, and wafers. Additionally, we account for mask errors by measuring pattern placement on the masks used for wafer exposure with a mask registration tool. Using this data, we perform a breakdown of the overlay errors into individual contributors, such as target overlay, device overlay, non-zero-offset (NZO) between target overlay and device overlay, and pattern placement errors on the masks. For each contributor, we examine sub-components in both the time domain (e.g., static, wafer-to-wafer and lot-to-lot) and the spatial domain (e.g., wafer-level and field-level) using novel analysis methods to identify the root causes of different effects. This approach enables us to pinpoint potential overlay improvements that remain uncorrected. For example, contributions, on field-level or micro-scale level, which are static over time, can be corrected by implementing a reticle writing correction on an updated mask. For contributions that are dynamically changing over time, this method can help to identify the root causes.