A Novel Optimal Sampling Digital PLL Design With High Performance and Alleviated Hardware for IOT Applications

ABSTRACT A key component of Internet of Things (IoT) nodes is the phase‐locked loop (PLL), yet power distribution remains an issue with the digital versions of these nodes. Reducing the high‐power distribution, which usually regulates the all‐digital PLL (ADPLL) power close to the digitally controlled oscillator (DCO), is essential for the development of the ultra‐low‐power ADPLL. The low‐level audio will reduce the active signal‐to‐noise ratio (SNR), when ADPLL is used in a communications system, causing significant inaccuracy and reducing the data rate. Therefore, it is vital to understand the trade‐off between phase noise, lock time performance, and variability in ADPLL. We present the improved design optimal sampling digital PLL (OS‐DPLL) for IoT applications in this paper. The proposed OS‐DPLL consists of a loop module (LM), ring oscillator (RO), first‐order digital loop filter (F‐DLF), divider chain, and bang–bang phase frequency detector (BBPFD), which uses the improved bang–bang approach. In addition, an efficient operating system is introduced to isolated operating modes, which provide standard bandwidth performance for sound and spectral purity in a closed phase mode. The simulation result determines the effectiveness of the proposed OS‐DPLL design based on power consumption, hardware utilization, and throughput.