A Broadband Doherty Power Amplifier Design with 22.4-dBm P_sat and 31% PAE in 45-nm SOI CMOS for 5G Application

The escalating data demands in contemporary wireless communications necessitate advanced power amplifier (PA) designs to meet stringent requirements of next-generation 5G millimeter-wave transceivers. This paper proposes an ultra-compact broadband Doherty Power Amplifier (DPA). Utilizing a transformer-based output combining and matching network, the proposed PA achieves a significantly smaller chip area compared to conventional Doherty PA design, as well as a low-loss output matching in the millimeter-wave frequency range. An inductor-based Wilkinson power divider is also employed for broadband power splitting. Furthermore, an adaptive bias network is adopted to enable real-time input signal tracking to optimize the linearity and efficiency of the PA, resulting in a high power-back-off efficiency. The simulation results demonstrate a saturated output power (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf>) of 22.4 dBm with a peak power-added efficiency (PAE) of 31%, and an output power of 16.7 dBm with a 6-dB back-off PAE of 16%. The DPA achieves an 8 GHz 1-dB P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf> bandwidth (BW) from 18.5 GHz to 28.5 GHz and a 13.6 GHz 3-dB small-signal bandwidth from 15.9 GHz to 29.5 GHz in 45nm SOI CMOS technology.