Design and Implementation of Low Power Energy Efficient 14T Hybrid Full Adder for Multiplier Applications

Since long, there is a rapid rise in energy-efficient appliances like electronics gadgets and microchip devices like health monitor wearable’s etc. The increased use of mentioned devices is built up via engineers to perform enhancement of the different type of circuits. Circuit with high efficiency, low power consumption and good speed having less chip-area have been explored. Full adder is a primary component that is used in arithmetic circuits, which shows a key role in present digital signal processing system. Some of arithmetic circuits are integrators, comparators, multipliers etc. Important thing of this device is, it’s a main part of the recent communication systems and complex path of many network circuits. Therefore, optimizing its performance in early stages enhances the system's overall performance with high efficiency and greater accuracy. Reducing transistor count can often lead to a decrease in processing speed or computational power. The Cadence Virtuoso tool in the study simulates this adder circuit at 0.8v–1.2v VDD using 90 nano meter CMOS technology, with a comparatively short delay and the average consumption of power for a 0.9 V supply was remarkably low. The current method proved to be more efficient than existing hybrid designs.