Emerging Field of NoC-Based Convolution Architecture with Systolic Arrays

Neural networks are widely used in image detection and identification applications because of their efficacy in handling complex problems. However, they require substantial memory bandwidth and CPU operations, limiting the performance of conventional CPUs. To address this challenge, researchers have developed an FPGA hardware accelerator for Convolution Neural Networks (CNNs). To enhance acceleration performance in CNNs, researchers have identified three key techniques: parallelization, memory optimization, and specialized data flow. A new network on-Chip paradigm was created by the researchers to reduce the off-chip memory Optimization according to researchers, a Network-on-Chip (NoC) architecture and Systolic Arrays (SA) have been created to enhance runtime, computational efficiency, and throughput while reducing off-chip memory traffic. In this paper recent trends in the NoC-Based CNN architecture have been represented.