Pipelined and Low-Power MAC Unit with Sparsity-Aware Encoding for Neural Network Applications

Multiply- Accumulate Units (MACs) are basic blocks in accelerators for neural networks, which need both high throughput and low power consumption to optimize matrix and vector computations. The present work proposes a new pipelined MAC architecture targeting neural network operations, focusing on issues concerning power efficiency and performance in computation. The proposed design exploits sparsity-aware methods to remove unnecessary operations with zero or redundant inputs, which reduces energy consumption significantly. An optimized pipeline architecture ensures decreased latency and increased throughput that makes the design suitable for real-time applications. Experiment results reveal that the proposed MAC unit performs very well in terms of power efficiency and processing speed compared to state-of-the-art architectures. This shows its suitability for energy-efficient neural network accelerators.