Impact of Voltage Class on SiC MOSFET Paralleled Chip Temperature Imbalance

This paper uses Monte-Carlo simulations to compare paralleling of 25 mΩ SiC MOSFET chips from two different voltage classes. Temperature dependent LTSpice simulations were performed with 5 TO-247-3 devices in parallel, rated for 650 V and 1200 V. Simulations were performed both with and without thermal coupling. We estimated the required nominal RDS(on) tolerance to achieve a mean junction temperature of 150°C ±7.5°C, with a maximum chip temperature imbalance of 10°C. We found a non-negligible difference between voltage classes, with the 1200 V devices having a 30%–50% increase (depending on configuration) in successful combinations over the 650 V devices without thermal-coupling, and a 12%–30% increase in successful combinations with thermal-coupling.