A 25-Gb/s Energy-Efficient PAM-4 Receiver Utilizing a Pulse Amplitude Comparator and Modified Summation Method

This article presents a 25 Gb/s pulse amplitude modulation 4-level (PAM-4) receiver that has only two comparators per data path for low power design. The receiver includes a pulse amplitude comparator that detects the amplitude difference in the differential input signal and compares it with the difference in the reference voltage. A continuous-time linear equalizer and decision feedback equalizer (DFE) are used to compensate for the channel loss and mitigate the inter-symbol interference. A modified summation method is introduced in the DFE to accommodate the reduced number of feedback signals owing to the decreased number of comparators. The proposed receiver is fabricated by a 28 nm CMOS process. At a supply voltage of 1 V and data rate of 25 Gb/s, the total power consumption is measured to be 10.298 mW. This results in an energy efficiency of 0.41 pJ/b. This represents an approximately 13% improvement compared with the PAM-4 receiver with the conventional structure.