Overcoming challenges raised by wafer load grid overlay fingerprints and correction per exposure management

Fab productivity is often constrained by photolithography cluster capacity. To maximize the use of scanners, layers are often run in both DCO (Dedicated Chuck Overlay) and MMO (Matched Machine Overlay) modes if desired specs can be achieved. For MMO overlay, delta scanner fingerprint is a significant contribution and is minimized by Baseliner product from ASML. For scanners, wafer back side and the wafer table interactions results in Wafer Load grid fingerprint (WLG) (figure 1). WLG is influenced by the roughness of the wafer back side and the wafer table status. Baseliner corrections generated from wafers with smooth backside adds WLG fingerprint to product wafers with rough back side. Corrections Per Exposure (CPE) can compensate WLG fingerprint differences between product and baseliner wafers and has been extensively investigated at ST. CPE implementation has been studied for several layers on two scanner combinations (Top and Bottom scanner). These correction sub-recipes are needed per product layout and per scanner couple to handle all sources of variability resulting in high metrology cost. In the light of this WLG fingerprint, different dynamic CPE application scenarios have been tested, from lot specific feed-forward to complete feedback strategy to find the optimum solution for production wafers. Additionally, these corrections need to be reset at each wafer table swap which leads to a lot of engineering management and productivity loss with reworks, because each CPE baseline per context needs the measurement of at least one lot to be re-learned. To optimize this, the team has worked on a global model to generate layout independent CPE corrections and enable faster processability recoveries post wafer table swap. Studied solutions are applied at ST on automotive grade products with nodes from 40nm to 18nm.