SnO Nanosheet Transistor with Remarkably High Hole Effective Mobility and More than Six Orders of Magnitude On-Current/Off-Current
Using novel SiO<sub>2</sub> surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µ<sub>eff</sub>) of more than 100 cm<sup>2</sup>/V·s and 31.1 cm<sup>2</sup>/V·s at hole densities (Q<sub>h</sub>) of 1 × 10<sup>11</sup> and 5 × 10<sup>12</sup> cm<sup>-2</sup>, respectively. To further improve the on-current/off-current (I<sub>ON</sub>/I<sub>OFF</sub>), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking I<sub>ON</sub>/I<sub>OFF</sub> of 6.9 × 10<sup>6</sup> and remarkable µ<sub>eff</sub> values of ~70 cm<sup>2</sup>/V·s and 20.7 cm<sup>2</sup>/V·s at Q<sub>h</sub> of 1 × 10<sup>11</sup> cm<sup>-2</sup> and 5 × 10<sup>12</sup> cm<sup>-2</sup>, respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µ<sub>eff</sub> that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small I<sub>ON</sub>/I<sub>OFF</sub> of 1.8 × 10<sup>4</sup> and a µ<sub>eff</sub> of only 6.1 cm<sup>2</sup>/V·s at 5 × 10<sup>12</sup> cm<sup>-2</sup> Q<sub>h</sub>. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn<sup>2+</sup> after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The I<sub>ON</sub>/I<sub>OFF</sub> ratio exceeding six orders of magnitude, remarkably high hole µ<sub>eff</sub>, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs).
Authors
- Kuan-Chieh Chen
- Pheiroijam Pooja (ORCID: https://orcid.org/0000-0001-5294-890X)
- Albert Chin (ORCID: https://orcid.org/0000-0001-6790-2437)
- Jiancheng Wu
Institutions
- National Yang Ming Chiao Tung University (TW)
Publication Details
- Journal
- Nanomaterials
- Published
- 2025-04-23
- DOI
- https://doi.org/10.3390/nano15090640
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.73
Funders
- Shanghai Educational Development Foundation
- National Science and Technology Council