Effect of different transistor technologies on physical design of arithmatic logic unit

Aims: The aim of this open source physical design tool is to observe the impact of miniaturization in transistor technology. Methods: This study encompasses the utilization of free or open-source software and the design processes involved in both digital and physical design phases within the realm of VLSI design. Additionally, open-source software was utilized as a synthesis tool during the physical design process. This approach allowed us to observe the impact of transistor technology shrinkage not only with licensed software but also with open-source alternatives. One distinguishing feature of this study lies in the verification of the design process through simulations, conducted both after the digital design phase and following the physical design phase. The physical design phase employed the open-source qflow software. Designs for 8-bit, 16-bit, and 32-bit Arithmetic Logic Units (ALUs) were synthesized using transistor technologies of 180nm and 350nm. Results: The results of the design experiments revealed that reducing the transistor technology scale for designs of the same bit length did not lead to a significant alteration in the number of standard cells comprising the design. However, the number of standard cells increased directly in proportion to the length. As technology continued to shrink, the physical area occupied by the design decreased, while Static Time Analysis (STA) also diminished concurrently with technology scaling. Conclusion: To promote the proliferation of VLSI design process-es, it is imperative to foster the development and utilization of open-source software. This approach facilitates the expansion of research and education in the field of VLSI design, ultimately augmenting the pool of skilled professionals in this domain