A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer

This paper presents a 7.68MSps 20kHz-BW nested continuous-time (CT) delta-sigma modulator (DSM) analog-to-digital converter (ADC). The nested DSM is composed of an inner analog CT DSM and a weighted multi-threshold MSB-pass quantization path. In the inner analog CT DSM, a negative-R-based cross-RC integrator structure is employed to reduce the resistance by 8×, thus improving area efficiency and alleviating parasitic issues introduced by large standard poly resistors. In the MSB-pass quantization path, several techniques including weighted counting, multi-threshold MSB-pass comparison, look-ahead comparison, and consecutive identical state detection are proposed. These techniques help to double the speed of the proposed nested DSM over the conventional nested DSM. Fabricated in a 180nm CMOS, the prototype DSM achieves SNR/SNDR/SFDR of 108.3dB/107.3dB/121.6dBc, with maximum resistance of only 179kΩ in the loop filter. The measured Schreier figure of merit (FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>S</roman></sub>) is 183.6dB.