Design of a Kickback Noise Reduction Technique for Dynamic Comparators based on XOR-NMOS Switches

To meet the rigorous demands for ultra-low power and miniaturized ADC converters, the XOR gates are used between regenerative nodes and comparator inputs to create an effected dynamic comparator. Traditionally, dynamic comparators have the advantage of consuming little power, offering high input impedance, and tolerating noise well. A significant drawback of these devices is their susceptibility to kickback noise, which significantly impacts the efficiency of their operations. Our creative approach focuses on noise reduction by carefully placing XOR gates and sampling switches between the comparator inputs and regeneration nodes to produce a strong noise isolation barrier. The efficacy of our method is demonstrated by validation through extensive simulations utilizing Cadence Virtuoso software within the context of cutting-edge 45 nm CMOS technology. This work represents a significant turning point in the scientific investigation of noise reduction strategies in analog circuitry. The proposed work consumed less power, delay and kickback noise compared to the existing works. In proposed work five different XOR based dynamic comparators are designed, the Pseudo NMOS XOR using NOR Dynamic comparator is achieved less kickback noise compared to the remaining designs. The 4T XOR dynamic comparator is consumed less power 0.097 nW and Pseudo NMOS XOR using NOR Dynamic comparator is contributed less delay 5.013 ns and kick back noise 168.2525 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{V}$</tex> compared to the other designs. The Pseudo NMOS XOR using NOR is the most efficient choice, as it provides the lowest kickback noise <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(168.2525\mu \mathrm{V})$</tex> while maintaining moderate power consumption <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(159.3\mu \mathrm{W})$</tex>. This balance of low noise and reasonable power usage makes it ideal for dynamic comparator applications.

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Published
2025-03-04
DOI
https://doi.org/10.1109/icvadv63329.2025.10961748
Citations
2
Primary Topic
CCD and CMOS Imaging Sensors
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article
Field-Weighted Citation Impact
1.46
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article

Design of a Kickback Noise Reduction Technique for Dynamic Comparators based on XOR-NMOS Switches

G. Snehalatha, Saiteja Chennoji, Sai Lohitha Yele, Sindhu Sri Bakna
2 citations
CCD and CMOS Imaging Sensors
1.46
article

Design of a Kickback Noise Reduction Technique for Dynamic Comparators based on XOR-NMOS Switches

G. Snehalatha, Saiteja Chennoji, Sai Lohitha Yele, Sindhu Sri Bakna
article en
2 citations

Abstract

To meet the rigorous demands for ultra-low power and miniaturized ADC converters, the XOR gates are used between regenerative nodes and comparator inputs to create an effected dynamic comparator. Traditionally, dynamic comparators have the advantage of consuming little power, offering high input impedance, and tolerating noise well. A significant drawback of these devices is their susceptibility to kickback noise, which significantly impacts the efficiency of their operations. Our creative approach focuses on noise reduction by carefully placing XOR gates and sampling switches between the comparator inputs and regeneration nodes to produce a strong noise isolation barrier. The efficacy of our method is demonstrated by validation through extensive simulations utilizing Cadence Virtuoso software within the context of cutting-edge 45 nm CMOS technology. This work represents a significant turning point in the scientific investigation of noise reduction strategies in analog circuitry. The proposed work consumed less power, delay and kickback noise compared to the existing works. In proposed work five different XOR based dynamic comparators are designed, the Pseudo NMOS XOR using NOR Dynamic comparator is achieved less kickback noise compared to the remaining designs. The 4T XOR dynamic comparator is consumed less power 0.097 nW and Pseudo NMOS XOR using NOR Dynamic comparator is contributed less delay 5.013 ns and kick back noise 168.2525 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{V}$</tex> compared to the other designs. The Pseudo NMOS XOR using NOR is the most efficient choice, as it provides the lowest kickback noise <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(168.2525\mu \mathrm{V})$</tex> while maintaining moderate power consumption <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(159.3\mu \mathrm{W})$</tex>. This balance of low noise and reasonable power usage makes it ideal for dynamic comparator applications.

Christian Medical College, Vellore (IN)
Affordable and clean energy
Openalex Percentile: Top 18%
CCD and CMOS Imaging Sensors
1.46
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Design of a Kickback Noise Reduction Technique for Dynamic Comparators based on XOR-NMOS Switches — G. Snehalatha, Saiteja Chennoji, et al. · (2025) | TGRS Research Map | TGRS