Built-In Error Resilient FPGA Based CIC Filter Design for Satellite Communication

Single-event and multi-bit effects are the result of radiation and ionized particles in extreme settings like space, which can lead to random failures on any electronic component. To keep the functionality of the device unaltered, these must be reduced. FPGA plays a vital role in satellite and aerospace applications in which dynamic reconfiguration essential. Cascaded Integration Comb (CIC) filters are mostly utilized in multidata signal processing and satellite communication systems as low pass filters in rate converter modules. The configuration memory of FPGA used to design CIC filter is affected with soft errors with single and multi-bit due to high radiation in higher altitude and different environment regions. The methods like triple modular redundancy (TMR) is very effective in overcoming single event transients and single-event upsets, but incur area three times of the original module. Scrubbing is a serial process method that goes over each word in memory in search of mistakes that need to be fixed. It entails a non-negligible Time to Detect (TTD) prior to repair, in which time further functionality could happen parallely and jeopardize the system. Thus, effective multi-bit error detection correction of configuration memory in FPGA is essential in maintaining the application to work for an extended time. In this research, built-in multi-bit error correction for FPGA configuration memory is proposed. The proposed work can replace time consuming scrubbing process and high area utilizing TMR for error tolerant design. To safeguard FPGA, a multi-bit error detection and correction system is performed by using multi dimensional parity with minimum area overhead. Furthermore, the suggested method can identify and rectify error when triggered by an interrupt manager reducing time to detect (TTD).