Pipeline and Wave Pipeline Based Comparative Analysis for FIR - Wallace Tree Multiplier for ECG Signal Denoising

Objective: Designing an effective multiplier assists in enhancing microprocessor system performance and complex digital signal processing. The main objective of this work is to design a 16 × 16 Wallace structure multiplier with a parallel prefix adder and evaluate the design's area, power performance, and utilization of resources using three distinct architectures: pipeline, wave pipeline, and hybrid pipeline. Methods: The 16 × 16 Wallace tree multiplier is designed using a parallel prefix adder in the Verilog HDL environment. The Wallace tree multiplier is integrated with a 3-tap FIR filter, and performances are evaluated through a distinct architecture by applying an ECG signal. It is suggested to use a hybrid wave-pipeline multiplier architecture to increase the Wallace tree multiplier's speed and reduce the delay. Delay optimization: In a hybrid pipelining system, the clock duration is relative to the maximum performance difference, whereas in a standard pipeline method, it is comparative to the greatest delay. In the hybrid pipeline multiplier, the last two rows of the partial products are added by parallel prefix adders (PPAs). To lower the delay, the hybrid multiplier uses the Han-Carlson adder for addition. Findings: The hybrid multiplier is executed in the FIR filter for ECG denoising in order to validate its performance. Xilinx ISE is used to synthesize the multiplier structures, whereas Verilog HDL is used for design. Comparing the suggested hybrid design to traditional pipelined designs, the outcome demonstrates that performance is increased while resource use and power optimization are reduced. Novelty: In this work, the hybrid pipeline approach has been applied to the existing Wallace multiplier architecture, and it offers better results in terms of power, area, and delay. The results indicate that the proposed hybrid design outperforms compared to traditional pipelined designs, achieving 48.83% improved delayed performance along with reduced resource usage and power consumption.