High volume manufacturing innovations for metal-oxide resist patterning

This paper investigates hardware innovations for lithography equipment used in patterning negative tone metaloxide resist (MOR), with a specific focus on improving yield for line-space structures at 28nm pitch and below. As semiconductor technology advances toward smaller nodes, maintaining high pattern fidelity while minimizing defects becomes increasingly difficult. MOR has emerged as a promising alternative to the traditionally used chemically amplified photoresist (CAR) to address issues with resolution limitations and pattern integrity, however the adoption of MOR has introduced new challenges to the industry. This study addresses these challenges by introducing hardware solutions that are designed to optimize MOR processes. Additionally, the study provides a comprehensive analysis of various developer techniques. Output parameters such as Critical Dimension (CD) stability, CD standard deviation, Line Edge Roughness (LER), Line Width Roughness (LWR), and defectivity are assessed following processing with 0.33 NA EUV using the new hardware and methods. The findings are further validated through electrical yield evaluations at 28nm pitch.