An integration engineering approach to material design and development

Looking back over the last 40 years of semiconductor lithography, the roadmaps of exposure tools and associated wavelength changes, and the large number of patterning materials and processes to increase resolution are well understood by this community. In this paper, a retrospective review of eclipsing technologies that had great impact on lithography requirements and processing will be presented, such as technologies from the realm of new device architecture, design and layout, new semiconductor process tooling, processes flows, and new materials that can and do intersect with lithography. Architecture changes are once again impacting today with production shifts to GAA (gate-all-around) and following with anticipated CFET (complementary field-effect transistor), stacked CFET, and 2D materials in the next five to seven years with associated changes in new materials, deposition, etch, and clean tools and associated processes. These architectures will be the primary drivers of semiconductor scaling for the foreseeable future. With the shrinking depth of focus and associated resist thickness shrinking, the process windows and specifications for most lithography layers are tightly tuned and customized. This leads to hyper tuning and little or no tolerance for variation or change once processes are set and masks are locked. This is where the primary focus on integration engineering approach or its equivalent DTCO (Design Technology Co-Optimization) comes into play.