mCFET inner spacer cavity etch: process development and challenges

Complementary Field-Effect Transistors (CFETs) offer a promising pathway for sub-1nm technology scaling through vertical stacking of n-FET and p-FET. This work focuses on optimizing the Inner Spacer Cavity (ISPC) etch process, a critical step in monolithic CFET integration using a Middle Dielectric Isolation (MDI) approach. The primary challenge is achieving uniform and selective SiGe etching to minimize top-to-bottom cavity depth variation and control gate length. An initial POR1(Process of reference) process exhibited significant loading effects due to Ge diffusion and concentration gradients, leading to non-uniform cavity depths. A new POR2 process, employing adjusted etch rates and hardware improvements, demonstrated reduced sensitivity to Ge% variations and improved uniformity. Further enhancements included Etch Front Correction (EFC) to achieve straight cavity geometries and reduced gate length variability. The impact of thermal budget was also investigated, revealing that lower thermal budgets improve ISPC cavity uniformity. To address remaining uniformity challenges, surface analysis using TOF-SIMS identified potential contaminants contributing to process variability. Statistical Process Control (SPC) utilizing Optical Critical Dimension (OCD) metrology was implemented for rapid characterization.