3D model assessment of a directional etch patterning process

Creating patterns in semiconductor logic chip manufacturing is no longer a matter of printing 2D lithographic images in photo resist followed by an etch or an implant. New methods are being used to manipulate the photolithographic image such as ion beam Ion Beam Etching (IBE) gas cluster beam (GCB). Predicting the shape and properties of the final hard mask image cannot be done with lithographic simulations alone. To model the patterning process, a hybrid approach is required that combines 2D photolithography and 3D film biases introduced by subsequent etching. Using this approach, a metal to via module can be analyzed to predict patterning rules and process windows. A Coventor SEMulator3D® model in combination with 2D resist contour images are used to predict the final shapes created in a hard mask layer. We examine the space error on regular patterns in 1D lines/space-pitches from 28 to 20 nm. Exposure is carried out on a 0.33 NA EUV scanner on negative tone resist. Subsequent Directional Etch (DE) adds an asymmetric bias to the line ends while and a smaller bias to the line widths. A SEMulator3D model can predict the final line/space and tip-to-tip (T2T) CDs, LCDUs after etching the resist pattern into a hard mask. It is shown that ADI shapes with T2T CD from 25 nm to 30 nm are reduced by IBE by 11 nm. The model employs a Monte-Carlo approach to capture the LCDU variability in T2T and trench width on multiple virtual wafers. We show that the model can be expanded to include a via level and used to predict the best layout design practices to ensure high yielding metal / via contacts. An early prediction of patterning performance can be made by combining 2D and 3D modeling capabilities where a directional etch is used. The model reflects the measured capabilities for CD and LCDU control. The observed tolerances are used to predict ground rules for a metal to contact level.