Patterning exploration of 16 nm pitch metal lines using spacer-is-dielectric EUV-based self-aligned double patterning

According to Imec’s research roadmap, from the A10 node onwards sub-20 nm pitch gratings and below are targeted for the most critical levels of nano-interconnects, while direct metal etch of Ru or alternative metals at local levels are expected to replace the Cu damascene metallization scheme. In this work, we demonstrate the feasibility of creating 16 nm pitch gratings in a Ru metal layer by combining EUV lithography with a self-aligned double patterning scheme in a spacer-is-dielectric approach, which enables variable metal line widths. We will present the dry etch process step improvements that have been made to enable this patterning approach, focusing on minimizing the pitch-walking, the line width and mask height uniformity and line edge roughness. The presented results highlight the potential of the semi-damascene integration approach using direct metal etch of Ru for further scaling towards even smaller pitches.